The present invention relates to a semiconductor device, and more particularly to a technology suitably applied to a semiconductor device having a package of a lead-on-chip (LOC) structure in which inner lead portions of leads are arranged on a major surface of a semiconductor chip sealed in a package body.
Among surface mount LSI (large-scale integrated circuit) packages, there is an LOC-structured package. This package has inner lead portions of leads arranged through an adhesive tape (i.e., adhesive and insulating sheet, the insulating sheet also being known as a base film) on a major surface (device-forming surface) of a semiconductor chip encapsulated with a molding resin, with the inner lead portions electrically connected to bonding pads of the semiconductor chip with Au wires. Packages of this kind of LOC structure are described in Japanese Patent Laid-Open No. 218139/1986 (which corresponds to U.S. Pat. No. 4,943,843) or No. 236130/1986, etc.
A technology for memory module stacking memory devices has been under study in recent years, to meet the demands for large-capacity memories (RAMs: random access memories), as engineering workstations and personal computers that are becoming smaller in size are required to process an increasingly large volume of data at high speed.
A known example of the stacked memory module has a structure in which several thin LSI packages such as TSOPs (thin small outline packages) and TSOJs (thin small outline J-lead packages) are stacked, and the corresponding leads of the upper and lower packages are connected by solder. Japanese Patent Laid-Open No. 175406-1993 describes a technology that facilitates stacking of leads of upper and lower packages by bending upward intermediate portions of leads of a TSOJ and extending part of that bent portion of the leads horizontally.